The present invention relates generally to memory devices, and, more particularly, to a controller for a memory device with a low-power retention mode.
In order to reduce power consumption, certain devices may be placed in a low-power mode when not active. In the low power mode some components may be supplied with a voltage that is lower than the normal operating voltage. Reducing the voltage across components can reduce leakage currents, leading to a reduction in power consumption by the device.
For some circuits, such as Static Random-Access Memory (SRAM) devices, it may be necessary to preserve logic values while the component is in a power-saving mode. SRAM is considered to be a form of volatile memory, as data will eventually be lost after power is removed. However, data stored in SRAM will typically persist for a short time after power is removed.
The present invention provides a memory controller and a method for retaining data yet saving power.